1. Technical Field
The present disclosure relates to a charge pump.
2. Description of Related Art
System-on-chip (SoC) is a very promising technique in today's increasingly precise chip application field. However, a clean and stable clock generator is required in each chip for providing a system clock signal to the more and more complicated structure. Thus, phase-locked loops (PLL) or delay-locked loops (DLL) are broadly used as system clock generators for generating a low-jitter clock signal that is unaffected by the fabricating process. Among all PLL structures, charge pump PLL is the most commonly used PLL thanks to its simple implementation and ease of mass production. In a charge pump PLL or DLL circuit, the most important issue is about the design of the charge pump circuit because charge pump is a very important analog block in a circuit. Accordingly, the design of a charge pump circuit affects the performance of a PLL or DLL circuit greatly, and how to improve the efficiency, precision, and operation rate of a charge pump circuit has become a major subject in PLL design.
FIG. 1 is a function block diagram of a conventional charge pump applied in a DLL 100. The DLL 100 has a phase detector (PD) 110, a charge pump 120, a filter 130, and a voltage-controlled delay line (VCDL) 140. FIG. 2 is a function block diagram of a conventional charge pump applied in a PLL 200. The PLL 200 has a PD 110, a charge pump 120, a filter 130, a voltage-controlled oscillator (VCO) 250, and a frequency divider 260. Implementations of the DLL 100 and the PLL 200 are well known by those having ordinary knowledge in the art therefore will not be described herein.
The charge pump 120 is a very common circuit block in the DLL 100 or the PLL 200. FIG. 3 is a timing diagram of signals in a conventional charge pump. The charge pump 120 charges or discharges the capacitive load of the filter 130 by using digital control signals UP and DN and converts the digital control signals UP and DN into an analog voltage O/P, so as to control the clock delay of the VCDL 140 (or the output frequency of the VCO 250). Thereby, a desired system clock signal is provided. However, when the switch 122 is turned off according to the control signal UP or the switch 123 is turned off according to the control signal DN, the problem of floating node may be caused between the switch 122 and the current source 121 or between the switch 123 and the current source 124. For example, if the switch 122 is turned off at this time, the node between the switch 122 and the current source 121 is floated because of the high impedance of the current source 121. As a result, the node between the switch 122 and the current source 121 may be affected by noises, and the problem of charge sharing may be produced.